The present invention relates to a sense amplifier driver circuit, and more particularly to a sense amplifier driver circuit for supplying a reduced power voltage to a sense amplifier for a dynamic semiconductor memory device.
In recent years, increases in capacity and high density of the dynamic semiconductor memory device has been promoted whilst scaling down devices used in the dynamic semiconductor memory device is remarkable. Scaling down the devices cause reduction in thickness of a capacitive film or dielectric film of a memory capacitor and a gate insulation film of a field effect transistor. The reduction in thickness of the capacitive film and the gate insulation film causes drop of withstand voltage of the memory capacitor and the field effect transistor. The drop in the withstanding voltage of the devices in the dynamic semiconductor memory device causes a reduction in reliability of the dynamic semiconductor memory device, In order to have avoided drop of the reliability of the device and also to have curtailed power consumption of the memory device, it had been proposed to supply a lower voltage than the power voltage Vcc to a memory cell array in he memory device.
FIG. 1 is a block diagram illustrative of a circuit configuration of the general dynamic semiconductor memory device, where an external power voltage is reduced for subsequent supply to memory cell arrays.
As shown in FIG. 1, one or more internal reduced voltage generation circuit 61 is provided on a chip for generating an internal reduced power voltage Vmt1. A plurality of memory cell arrays 62-1, 62-2, 62-3, - - - 62-N are also provided on the chip. An output side of the internal reduced voltage generation circuit 61 is connected to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N. FIG. 2 is a circuit diagram illustrative of a differential amplifier circuit in the internal reduced voltage generation circuit shown in FIG. 1. The internal reduced voltage generation circuit 61 comprises a differential amplifier circuit 63 and a p-channel MOS field effect transistor Q8. One input of the differential amplifier circuit 63 receives a reference voltage Vref as a reference to an internal reduction voltage level. Another input of the differential amplifier circuit 63 receives the internal reduced power voltage Vmt1 as the output from the internal reduced voltage generation circuit 61. An output terminal of the differential amplifier circuit 63 is connected to a gate of the p-channel MOS field effect transistor Q8. A source of the p-channel MOS field effect transistor Q8 is connected to a power voltage line which supplies a power voltage Vcc. A drain of the p-channel MOS field effect transistor Q8 is connected to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N, so that the internal reduced power voltage Vint1 is supplied from the drain of the p-channel MOS field effect transistor Q8 to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N. Namely, the internal reduced voltage generation circuit 61 outputs the internal reduced power voltage Vint1. Parasitic capacitances R11, R12, R13, - - - R1N exit on the interconnection between the internal reduced voltage generation circuit 61 and the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N. Those parasitic capacitances R11, R12, R13, - - - R1N reduce the voltage levels to be supplied to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N. The actual voltages supplied to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N are thus lower than the internal reduced power voltage Vint1. For example, the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N are supplied with voltages Vint11, Vint12, Vint13, - - - Vint1N.
The memory cell arrays 62-1, 62-2, 62-3, - - - 62-N have the same circuit configuration, for which reason only the circuit configuration of the memory cell array 62-1 will be described whilst the circuit configuration of the other memory cell arrays 62-2, 62-3, - - - 62-N will be omitted. The memory cell array 62-1 has a plurality of alignments of memory cells MC, sense amplifiers SA for every alignments of the memory cells MC, a plurality of word lines WL and a plural pairs of memory cell digit lines DT and DN or bit lines. Each of the memory cell MC is positioned at one of cross points of the word lines WL and the memory cell digit lines DT. The memory cell MC is connected to both one word line WL and one memory cell digit line DT, a crossing point of which is a position where the memory cell MC is provided. For example, a memory cell MC0 is connected to both a word line WL0 and a memory cell digit line DT0. Although illustration is omitted, memory cells are provided which are connected to the memory cell digit lines DN.
Further, sense amplifier digit lines BT and BN are also provided. The sense amplifier digit lines BT and BN are connected in series through n-channel MOS field effect transistors Q7 to the memory cell digit lines DT and DN. Gates of the n-channel MOS field effect transistors Q7 are connected to a gate control line TG. For example, the sense amplifier digit line DT0 is connected through the n-channel MOS field effect transistor Q7 to the memory cell digit line DT0. The sense amplifier digit line BN0 is connected through the n-channel MOS field effect transistor Q7 to the memory cell digit line DN0.
Each of the sense amplifiers SA is connected to a corresponding pair of the sense amplifier digit lines BT and BN. For example, the sense amplifier SA0 is connected to the sense amplifier digit lines BT0 and BN0.
All of the sense amplifiers SA are connected to power supply lines SAP and SAN. The power supply line SAN is connected in series to a ground line through an n-channel MOS field effect transistor 64 having a gate, to which a control signal (SAN. This ground line supplies a ground potential as a reference voltage GND. The other power supply line SAP is connected through a p-channel MOS field effect transistor Q9 and the interconnection to the internal reduced voltage generation circuit 61. The p-channel MOS field effect transistor Q9 has a gate receiving a control signal .PHI.SAP. Namely, the voltage Vint11, which is lower than the internal reduced power voltage Vmt1, is supplied through the p-channel MOS field effect transistor Q9 to the memory cell array 62-1. Each of the sense amplifiers SA is operated to sense a potential difference or a voltage difference between the paired sense amplifier digit lines BT and BN connected with the sense amplifier SA so that the sense amplifier SA is then operated to amplify the sensed potential difference.
The following descriptions will focus on operations of the dynamic semiconductor memory device shown in FIG. 1. FIG. 3 is a waveform explaining operations of the dynamic semiconductor memory device shown in FIG. 1.
When one of the word lines WL, for example, the word line WL0 is selected, a potential of the selected word line WL0 is increased up to a predetermined level, whereby the transistor of the memory cell MC0 turns ON to allow stored information in the memory cell MC0 to be transmitted onto the memory cell digit line DT0. If high level has been stored in the memory cell MC0, as the potential increase of the word line WL0 causes a slight increase in potential of the memory cell digit line DT0. At this time, also the potential of the control line TG connected to the gate of the n-channel MOS field effect transistor Q7 is fixed in high level, and thus the n-channel MOS field effect transistor Q7 between the sense amplifier digit line BT0 and the memory cell digit line DT0 remains in ON state. Therefore, the potential is the same between the memory cell digit line DT0 and the sense amplifier digit line BT0. Accordingly, a potential increase of the memory cell digit line DT0 causes a corresponding potential increase of the sense amplifier digit line BT0.
Thereafter, the potential level of the control line TG connected to the gates of the n-channel MOS field effect transistors Q7 is reduced down to the low level. Further, the control signal .PHI.SAP becomes low level, whilst the control signal .PHI.SAN becomes high level, whereby the sense amplifier SA is activated to commence its sense operation. Namely, the sense amplifier SA0 is operated to sense and amplify a slight difference in potential between the paired sense amplifier digit lines BT0 and BN0 connected to the sense amplifier SA0. As a result of the amplification by the sense amplifier SA0, the potential of the sense amplifier digit line BT0 becomes close to the internal reduced voltage level Vref1, whilst the potential of the sense amplifier digit line BN0 becomes close to the reference voltage GND. Once the potentials of the sense amplifier digit lines BT0 and BN0 reach the internal reduced voltage level Vref1 and the reference voltage GND respectively, the sense amplification operation is completed. At the same time when the sense amplification operation is completed, the potential of the control line TG is risen up to the predetermined level to turn the n-channel MOS field effect transistor Q7 ON so that the paired memory cell digit lines DT0 and DN0 are made connected to the paired sense amplifier digit lines BT0 and BN0 respectively, whereby re-store operation is carried out to re-write data into a capacitor of the memory cell MC0. As a result of the re-writing operation, the potential of the memory cell digit line DT0 is made close to the internal reduced voltage Vref1, whilst the potential of the memory cell digit line DN0 reaches the reference voltage GND, whereby charges are accumulated in the capacitor of the memory cell MC0.
The above described conventional dynamic semiconductor memory device is, however, engaged with the following problems.
As being appeared from FIG. 3, when relatively large currents flow through the power supply line SAP such as the sense amplification operation and the re-store operation, a large drop of the internal reduced power voltage level appears. This voltage level drop of the internal reduced power voltage level causes delay in operational speeds in the sense amplification operation and he re-store operation. Even if in order to solve this problem, the width of the interconnection which interconnecting the internal reduced power voltage generation circuit Vint and the individual memory cell arrays are widen to reduce the resistance of the interconnection, another problem with layout is raised due to an enlargement of area of the interconnection.
The transistor such as the p-channel MOS field effect transistor Q9 connected through the interconnection to the internal reduced power voltage generation circuit Vint is required to satisfy the conduction that a difference in potential between source and drain is small, for which reason in order to flow a large current, it is required to enlarge the size of the transistor.
It is preferable to reduce the internal reduced voltage level Vref1 as low as possible for improvement in reliability of the device and for reduction in power consumption. However, the reduction in internal reduced voltage level Vref1 raises a problem in delay of the sense amplifying operations of the sense amplifier. In order to have solved this problem with the delay in sense amplifying operations of the sense amplifier, an over-drive system for a driving technique of the sense amplifier was proposed. Those conventional over-drive techniques are disclosed, for example, in Japanese laid-open patent publications Nos. 5-135579, 9-63271 and 9-120675.
FIG. 4 is a block diagram illustrative of a circuit configuration of the dynamic semiconductor memory device operable in over-drive system. The circuit configuration of the over-drive dynamic semiconductor memory device shown in FIG. 4 differs from the general dynamic semiconductor memory device shown in FIG. 1 in the light of further provision of a secondary internal reduced voltage generation circuit 91 which generates a second internal reduced voltage Vint2. One input of the secondary internal reduced voltage generation circuit 91 is applied with a second voltage Vref2 which is higher in potential than the first voltage Vref2 applied to the first internal reduced voltage generation circuit 61. An output of the secondary internal reduced voltage generation circuit 91 is connected through a second interconnection to the memory cell arrays. In each of the memory cell arrays, a p-channel MOS field effect transistor Q10 is further provided which is connected in series between the second interconnection and the power supply line SAP of the memory cell array. Namely, the secondary internal reduced voltage generation circuit 91 is connected through the second interconnection to the power supply line SAP of the memory cell array. The second interconnection also has a parasitic capacitance as the first interconnection. A gate of the p-channel MOS field effect transistor Q10 is applied with a control signal .PHI.SAP2 which is different from a control signal .PHI.SAP1 applied to the gate of the n-channel MOS field effect transistor Q9.
As a modification to the conventional over-drive dynamic semiconductor memory device shown in FIG. 4, it is possible that a power voltage line which supplies a power voltage Vcc is connected directly to the p-channel MOS field effect transistor Q10 without, however, providing the above secondary internal reduced voltage generation circuit 91.
With reference again to FIG. 4, the conventional circuit configuration of the over-drive dynamic semiconductor memory device will be described in more detail.
First and second internal reduced voltage generation circuits 61 and 91 are provided on a chip for generating first and second internal reduced power voltages Vint1 and Vint2 respectively. A plurality of memory cell arrays 62-1, 62-2, 62-3, - - - 62-N are also provided on the chip. An output side of the first internal reduced voltage generation circuit 61 is connected to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N. An output side of the second internal reduced voltage generation circuit 91 is connected to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N. The first internal reduced voltage generation circuit 61 comprises a differential amplifier circuit 63 and a p-channel MOS field effect transistor Q8. The second internal reduced voltage generation circuit 91 also comprises a differential amplifier circuit and a p-channel MOS field effect transistor.
One input of the differential amplifier circuit 63 of the first internal reduced voltage generation circuit 61 receives a first reference voltage Vref1 as a first reference to a first internal reduction voltage level. Another input of the differential amplifier circuit 63 of the first internal reduced voltage generation circuit 61 receives the first internal reduced power voltage Vint1 as the first output from the first internal reduced voltage generation circuit 61. An output terminal of the differential amplifier circuit 63 of the first internal reduced voltage generation circuit 61 is connected to a gate of the p-channel MOS field effect transistor Q8 of the first internal reduced voltage generation circuit 61. A source of the p-channel MOS field effect transistor Q8 of the first internal reduced voltage generation circuit 61 is connected to a power voltage line which supplies a power voltage Vcc. A drain of the p-channel MOS field effect transistor Q8 of the first internal reduced voltage generation circuit 61 is connected to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N, so that the first internal reduced power voltage Vint1 is supplied from the drain of the p-channel MOS field effect transistor Q8 to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N. Namely, the first internal reduced voltage generation circuit 61 outputs the first internal reduced power voltage Vint1.
One input of the differential amplifier circuit of the second internal reduced voltage generation circuit 91 receives a second reference voltage Vref2 as a second reference to a second internal reduction voltage level. Another input of the differential amplifier circuit of the second internal reduced voltage generation circuit 91 receives the second internal reduced power voltage Vint2 as the second output from the second internal reduced voltage generation circuit 91. An output terminal of the differential amplifier circuit of the second internal reduced voltage generation circuit 91 is connected to a gate of the p-channel MOS field effect transistor of the second internal reduced voltage generation circuit 91. A source of the p-channel MOS field effect transistor of the second internal reduced voltage generation circuit 91 is connected to the power voltage line which supplies the power voltage Vcc. A drain of the p-channel MOS field effect transistor of the second internal reduced voltage generation circuit 91 is connected to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N, so that the second internal reduced power voltage Vint2 is supplied from the drain of the p-channel MOS field effect transistor to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N. Namely, the second internal reduced voltage generation circuit 91 outputs the second internal reduced power voltage Vint2.
Parasitic capacitances R11, R12, R13, - - - R1N exit on the first interconnection between the first internal reduced voltage generation circuit 61 and the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N. Those parasitic capacitances R11, R12, R13, - - - R1N reduce the voltage levels to be supplied to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N. The actual voltages supplied to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N are thus lower than the first internal reduced power voltage Vint1. For example, the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N are supplied with voltages Vint11, Vint12, Vint13, - - - Vint1N which have been transmitted through the second interconnection from the first internal reduced voltage generation circuit 61.
Parasitic capacitances R21, R22, R23, - - - R2N exit on the second interconnection between the second internal reduced voltage generation circuit 91 and the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N. Those parasitic capacitances R21, R22, R23, - - - R2N reduce the voltage levels to be supplied to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N. The actual voltages supplied to the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N are thus lower than the second internal reduced power voltage Vint2. For example, the memory cell arrays 62-1, 62-2, 62-3, - - - 62-N are supplied with voltages Vint21, Vint22, Vint23, - - - Vint2N which have been transmitted through the second interconnection from the first internal reduced voltage generation circuit 91.
The memory cell arrays 62-1, 62-2, 62-3, - - - 62-N have the same circuit configuration, for which reason only the circuit configuration of the memory cell array 62-1 will be described whilst the circuit configuration of the other memory cell arrays 62-2, 62-3, - - - 62-N will be omitted. The memory cell array 62-1 has a plurality of alignments of memory cells MC, sense amplifiers SA for every alignments of the memory cells MC, a plurality of word lines WL and a plural pairs of memory cell digit lines DT and DN or bit lines. Each of the memory cell MC is positioned at one of cross points of the word lines WL and the memory cell digit lines DT. The memory cell MC is connected to both one word line WL and one memory cell digit line DT, a crossing point of which is a position where the memory cell MC is provided. For example, a memory cell MC0 is connected to both a word line WL0 and a memory cell digit line DT0. Although illustration is omitted, memory cells are provided which are connected to the memory cell digit lines DN.
Further, sense amplifier digit lines BT and BN are also provided. The sense amplifier digit lines BT and BN are connected in series through n-channel MOS field effect transistors Q7 to the memory cell digit lines DT and DN. Gates of the n-channel MOS field effect transistors Q7 are connected to a gate control line TG. For example, the sense amplifier digit line BT0 is connected through the n-channel MOS field effect transistor Q7 to the memory cell digit line DT0. The sense amplifier digit line BN0 is connected through the n-channel MOS field effect transistor Q7 to the memory cell digit line DN0.
Each of the sense amplifiers SA is connected to a corresponding pair of the sense amplifier digit lines BT and BN. For example, the sense amplifier SA0 is connected to the sense amplifier digit lines BT0 and BN0.
All of the sense amplifiers SA are connected to power supply lines SAP and SAN. The power supply line SAN is connected in series to a ground line through an n-channel MOS field effect transistor 64 having a gate, to which a control signal .PHI.SAN. This ground line supplies a ground potential as a reference voltage GND.
The other power supply line SAP is connected through a p-channel MOS field effect transistor Q9 and the first interconnection to the first internal reduced voltage generation circuit 61. The p-channel MOS field effect transistor Q9 has a gate receiving a first control signal .PHI.SAP1. Namely, the voltage Vint11, which is lower than the first internal reduced power voltage Vint1, is supplied through the p-channel MOS field effect transistor Q9 to the memory cell array 62-1. The other power supply line SAP is also connected through a p-channel MOS field effect transistor Q10 and the second interconnection to the second internal reduced voltage generation circuit 91. The p-channel MOS field effect transistor Q10 has a gate receiving a second control signal .PHI.SAP2. Namely, the voltage Vint21, which is lower than the second internal reduced power voltage Vint2, is supplied through the p-channel MOS field effect transistor Q10 to the memory cell array 62-1.
Each of the sense amplifiers SA is operated to sense a potential difference or a voltage difference between the paired sense amplifier digit lines BT and BN connected with the sense amplifier SA so that the sense amplifier SA is then operated to amplify the sensed potential difference.
The following descriptions will focus on operations of the above over-drive dynamic semiconductor memory device shown in FIG. 4. FIG. 5 is a waveform explaining operations of the over-drive dynamic semiconductor memory device shown in FIG. 4. The operations of the over-drive dynamic semiconductor memory device shown in FIG. 4 is basically the same as the operation of the dynamic semiconductor memory device shown in FIG. 1, except that voltage supplied onto the power supply line is different between the sense amplification operation and re-store operation. Namely, for the sense amplification operation, a second internal reduced voltage level Vint2 is supplied whilst for the re-store operation, the first internal reduced voltage level Vint1 which is lower than the second internal reduced voltage level Vint2 is reduced. The detailed descriptions will be made hereafter.
When one of the word lines WL, for example, the word line WL0 is selected, a potential of the selected word line WL0 is increased up to a predetermined level, whereby the transistor of the memory cell MC0 turns ON to allow stored information in the memory cell MC0 to be transmitted onto the memory cell digit line DT0. If high level has been stored in the memory cell MC0, as the potential increase of the word line WL0 causes a slight increase in potential of the memory cell digit line DT0. At this time, also the potential of the control line TG connected to the gate of the n-channel MOS field effect transistor Q7 is fixed in high level, and thus the n-channel MOS field effect transistor Q7 between the sense amplifier digit line BT0 and the memory cell digit line DT0 remains in ON state. Therefore, the potential is the same between the memory cell digit line DT0 and the sense amplifier digit line BT0. Accordingly, a potential increase of the memory cell digit line DT0 causes a corresponding potential increase of the sense amplifier digit line BT0.
Thereafter, the potential level of the control line TG connected to the gates of the n-channel MOS field effect transistors Q7 is reduced down to the low level. Further, the second control signal .PHI.SAP2 applied to the gate of the p-channel MOS field effect transistor Q10 becomes low level to turn the p-channel MOS field effect transistor Q10 ON, whilst the control signal .PHI.SAN1 applied to the gate of the p-channel MOS field effect transistor Q9 becomes high level to turn the p-channel MOS field effect transistor Q9 OFF. The voltage Vint2 reduced by the parasitic capacitances R21, R22, R23, - - - R2N from the second internal reduced voltage level Vint2 is then supplied through the p-channel MOS field effect transistor Q10 onto the power supply line SAP. The sense amplifier SA is activated to commence its sense operation. The power supply line SAP is connected to the second internal reduced voltage generation circuit Vint21 through the p-channel MOS field effect transistor Q10, for which reason in the sense amplification operation, the power voltage level supplied to the sense amplifier SA0 is the second internal reduced voltage level Vint2 or Vref2. Thus, the sense amplifier SA0 is operated to sense and amplify a slight difference in potential between the paired sense amplifier digit lines BT0 and BN0 connected to the sense amplifier SA0. As a result of the amplification by the sense amplifier SA0, the potential of the sense amplifier digit line BT0 becomes close to the internal reduced voltage level Vref2, whilst the potential of the sense amplifier digit line BN0 becomes close to the reference voltage GND. Once the potentials of the sense amplifier digit lines BT0 and BN0 reach the internal reduced voltage level Vref2 and the reference voltage GND respectively, the sense amplification operation is completed. At the same time when the sense amplification operation is completed, the potential of the control line TG is risen up to the predetermined level to turn the n-channel MOS field effect transistor Q7 ON. The first control signal .PHI.SAP1 applied to the gate of the p-channel MOS field effect transistor Q9 becomes low level to turn the p-channel MOS field effect transistor Q9 ON, whilst the second control signal .PHI.SAP2 applied to the gate of the p-channel MOS field effect transistor Q10 becomes high level to turn the p-channel MOS field effect transistor Q10 OFF. The voltage Vint11 reduced by the parasitic capacitances R11, R12, R13, - - - R1N from the first internal reduced voltage level Vint1 is then supplied through the p-channel MOS field effect transistor Q9 onto the power supply line SAP. The paired memory cell digit lines DT0 and DN0 are made connected to the paired sense amplifier digit lines BT0 and BN0 respectively, whereby re-store operation is carried out to re-write data into a capacitor of the memory cell MC0. As a result of the rewriting operation, the potential of the memory cell digit line DT0 is made close to the internal reduced voltage Vref1, whilst the potential of the memory cell digit line DN0 reaches the reference voltage GND, whereby charges are accumulated in the capacitor of the memory cell MC0.
The over-drive system allows a higher power voltage to be supplied to the memory cells in the sense amplification operation for ensuring high speed performance and also allows a lower power voltage to be supplied to the memory cells in the re-store operation for improvement in the reliability of the memory cells and also for reduction in charge and discharge currents flowing on the memory cell digit lines hereby to reduce power consumption.
The above described conventional over-drive system is, however, engaged with the following problems. It is necessary that the two internal reduced power voltage generation circuits are connected through first and second interconnections to each of the memory cell arrays. This means that the necessary area for layout of the interconnections interconnecting the internal reduced power voltage generator circuit and the individual memory cell arrays is double of the over-drive free dynamic semiconductor memory device.
Further, each of the memory cell arrays has two transistors which are connected through the two interconnections to the two internal reduced power voltage generation circuits. This means that the necessary area for layout of the transistors connected through the interconnections to the internal reduced power voltage generation circuits is double of the overdrive free dynamic semiconductor memory device.
In the above circumstances, it had been required to develop a novel sense amplifier driver circuit free from the above problem.